The present invention is generally directed to a method and apparatus for producing via holes in polymer dielectrics without the use of a mask. More particularly, the present invention is related to a packaging method for electronic integrated circuit chips, particularly very large scale integrated circuit (VLSI) devices. The method and apparatus of the present invention produces via openings in a polymer film overlay and thereby provides a means for electrically connecting, through the vias formed, a plurality of circuit chips disposed on a substrate. It is also noted that the present invention provides significant advantages in a system of microchip packaging.
In the packaging of very large scale integrated circuit devices, a great deal of space is taken up by mechanisms for interconnecting one chip to an adjacent device. This makes the packaging of integrated circuit devices and electronic components based thereon larger than necessary. As a result of this, many individuals are involved in the development of so-called wafer-scale integration processes. However, the efforts expended in these directions have generally tended to be limited by the problem of yield. Because a certain number of chips or dies on a wafer are often found to be defective, the number of wafers that are produced that are completely usable is generally lower than is desirable. Furthermore, there still exists the problem of interconnecting the various chips on a wafer and the concomitant problem of testing a large system such as results when a number of highly complicated individual integrated circuit components are interconnected. Accordingly, it is seen that it would be very desirable to be able to construct wafer-scale integrated circuit packages from individual, easily testable integrated circuit chips. It is to this end that the present invention is directed.
More particularly, the present invention is directed to a method and apparatus for producing via openings in a polymer film overlay. This film typically covers a plurality of integrated circuit chips disposed adjacent to one another on an underlying substrate. The polymer film provides an insulative layer to facilitate interconnection of these individual circuit chips through the via openings produced in accordance with the present invention. Furthermore, a significant advantage of the system described is the ability to remove one or more of these interconnection layers so as to provide a multitude of arrangement and testing capabilities. It is noted also that the method of the present invention is also applicable even if only a single chip is present.
Polymer dielectrics are finding increased use in multichip packaging approaches because such dielectrics are easily applied at low temperatures and they result in relatively thick coatings having a low dielectric constant. More particularly, the problem addressed by the present invention is the production of holes in such polymer layers for the purpose of connecting metallization on the top of the polymer to metallization under the polymer dielectric. In the case of a removable polymer overlay layer, the interconnection is from chip pads under the polymer layer to interconnect metallization on top of the polymer layer.
One method for providing via holes in a polymer is to apply a metal mask to the top surface of the polymer by metal deposition. For example, a 1,000 angstrom thick layer of titanium can be applied. The titanium is then processed by photolithographic methods and holes are etched in the titanium where via holes are desired. The polymer is then etched in an oxygen plasma. The oxygen plasma does not attack the titanium, but does attack the exposed polymer. This approach has several shortcomings in many applications, including the present one. For example, holes that result would have very straight sidewalls if ion beam etching is used. Subsequent metallization over the sharp sidewall edge often results in breaks in metallization at the edge and also results in a low yield process. This process is exacerbated as thickness of the polymer is increased. Sharp sidewalls cannot be accommodated in polymer thicknesses of 12 to 25 microns. If a plasma barrel etcher is used, undercutting and a resulting "barrel" form to the via hole can result in a hole where the top of the hole is actually smaller than the middle. Such an opening cannot be metallized properly. By very careful control of the etching time, outward sloping sidewalls can be achieved but with the concomitant risk that the opening will not go completely through the polymer and leave a clean bottom surface for electrical connection. Finally, such processes involve a substantial number of steps: depositing the metal mask which involves first cleaning the polymer for good adhesion then depositing a photoresist, drying the resist, exposing the resist, developing the resist, hard-baking the resist, then etching holes in the metal mask. This is followed by a carefully controlled plasma etch step which is highly dependent on the temperature of the etchant and gas pressures. Additionally, the metal mask layer must be removed in order to assure good adhesion between the conductor metallization which is to be applied next and the polymer. Finally, the metal mask which is applied is opaque. This rules out the possibility of using a vision system to identify pad positions on chips and then to adaptively define the via hole position. This ability is extremely desirable in high density interconnect methods which involve a polymer overlay layer. In such methods, the chips are placed on the substrate with relatively low accuracy. A manual or automated scan system identifies the actual pad positions and slightly modifies the original artwork to match the actual pad positions. It is a problem to have a system in which the pads cannot be seen because the mask used is opaque. An additional problem using an etch mask occurs if there are pinholes, either in the mask or in the resist. In either case, the result is unwanted via openings.
An alternative approach to forming via openings is to spin or spray polyimide on a substrate and only partially cure the polyimide. Subsequently, the polyimide is coated with a photoresist and the resist is developed. In the partially cured state, the polyimide is also attacked by the developer and via holes can be etched in thin films of polyimide. This process is not satisfactory for thick films of polyimide since entrapped water vapor in the polymer cannot escape. The limit on this process is a thickness of 5 microns. In addition, this process could not be used to produce an overlay layer across the space between two chips since there is no supportive film involved in spraying or spin methods. Photosensitive polyimides are becoming available, but they suffer the same problems of thickness and inability to provide a continuous film across two chips.
A method which can be used to provide via openings through relatively thick layers of polymer involves patterning the lower layer of metallization and building up by electroplating the areas where vias are desired. This essentially leaves pillars of conductor material where the via is desired. Polymer material is them sprayed or spun on the substrate in multiple coats with sufficient curing between coats to allow solvent and byproducts of the curing process to escape. Enough coats are built up to completely cover the conductors, but to barely cover the via pillars. Short etch or even mechanical lapping is sufficient to uncover the top surface of the via pillars. While this method results in a planar surface, it involves a large number of steps and, again, cannot be used where an overlay layer must bridge a gap between two chips.
In addition to the problems associated with the approaches described above for providing via holes, it is noted that these processes cannot be achieved without the use of wet processing; that is, wet chemistry must be employed for developing a photoresist for etching of the mask or for the plating of the via areas. A distinguishing characteristics of the disclosed invention is that it is achieved using a plasma etch, which is a dry process.
The use of lasers for drilling holes is another method employed to provide vias. Typically, a laser is used in a pulse mode to evaporate material wherever the laser energy is concentrated. Very short pulses heat the material to the point that it vaporizes. This approach, however, is not satisfactory for providing via holes in the circumstances contemplated herein. First, in such methods, the underlying pads are damaged by energy which is sufficient to vaporize the polymer. It is unacceptable to damage the underlying pads. Second, the process is relatively slow in that several pulses are required. In an interconnect system, a large number of holes is required so that slow processes are again unacceptable.